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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This file demonstrates how to use the mcdma driver on the Xilinx AXI MCDMA core (AXI MCDMA) to transfer packets in polling mode. </p>
<p>This examples shows how to do multiple packets and multiple BD's per packet transfers.</p>
<p>H/W Requirements: In order to test this example at the h/w level AXI MCDMA MM2S should be connected to the S2MM channel.</p>
<p>System level considerations for Zynq UltraScale+ designs: On ZU+ MPSOC for PL IP's 3 different ports are available HP, HPC and ACP.</p>
<p>The explanation below talks about HPC and HP port.</p>
<p>HPC design considerations: ZU+ MPSOC has in-built cache coherent interconnect(CCI) to take care of Coherency through HPC port. CCI is only support at EL1 NS level. Following needs to be done by the system components before running the example- 1) Snooping should be enabled in the S3 (0xFD6E4000) 2) Mark the DDR memory being used for buffers as outer-shareable. translation_table.S. .set Memory, 0x405 | (2 &lt;&lt; 8) | (0x0).</p>
<p>It is recommended to use HPC to make use of H/W coherency feature.</p>
<p>HP design considerations: The example uses un-cached memory for buffer descriptors and uses Normal memory for buffers..</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date       Changes
----- ---- --------   -------------------------------------------------------
1.0      adk  18/07/2017 Initial Version.
1.2      rsp  07/19/2018 Read channel count from IP config.
      rsp  08/17/2018 Fix typos and rephrase comments.
      rsp  08/17/2018 Read Length register value from IP config.
1.3   rsp  02/05/2019 Remove snooping enable from application.
      rsp  02/06/2019 Programmatically select cache maintenance ops for HPC
                      and non-HPC designs. In Rx remove arch64 specific dsb
                      instruction by performing cache invalidate operation
                      for all supported architectures.
1.7   sa   08/12/22  Updated the example to use latest MIG cannoical define
                        i.e XPAR_MIG_0_C0_DDR4_MEMORY_MAP_BASEADDR.
1.8   sa   09/29/22  Fix infinite loops in the example.
1.9      aj   07/19/23   Updated the example to support the system device tree
                         flow
</pre><hr/>
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Functions</h2></td></tr>
<tr class="memitem:a840291bc02cba5474a4cb46a9b9566fe"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xmcdma__polled__example_8c.html#a840291bc02cba5474a4cb46a9b9566fe">main</a> (void)</td></tr>
<tr class="memdesc:a840291bc02cba5474a4cb46a9b9566fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Main function.  <a href="#a840291bc02cba5474a4cb46a9b9566fe">More...</a><br/></td></tr>
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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">int main </td>
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          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
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<p>Main function. </p>
<p>This function is the main entry of the tests on DMA core. It sets up DMA engine to be ready to receive and send packets, then a packet is transmitted and will be verified after it is received via the DMA.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">None</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if test passes</li>
<li>XST_FAILURE if test fails.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__mcdma.html#gaded8280c89d619daddc45d217358a319">XMcDma_CfgInitialize()</a>, and <a class="el" href="group__mcdma.html#ga62a895328daf1573051668904d39570e">XMcdma_LookupConfig()</a>.</p>

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